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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

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whitequark 2018-12-05 04:50:38 +00:00
parent 12596b5003
commit 9ef078848a
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13
tests/lut/check_map.ys Normal file
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design -save preopt
simplemap
techmap -map +/gate2lut.v -D LUT_WIDTH=4
select -assert-count 1 t:$lut
design -stash postopt
design -copy-from preopt -as preopt top
design -copy-from postopt -as postopt top
equiv_make preopt postopt equiv
prep -flatten -top equiv
equiv_induct
equiv_status -assert