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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

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whitequark 2018-12-05 04:50:38 +00:00
parent 12596b5003
commit 9ef078848a
10 changed files with 133 additions and 0 deletions
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1
techlibs/common/Makefile.inc
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@ -25,5 +25,6 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))

87
techlibs/common/gate2lut.v Normal file
View file

@ -0,0 +1,87 @@
(* techmap_celltype = "$_NOT_" *)
module _90_lut_not (A, Y);
input A;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b01)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_OR_" *)
module _90_lut_or (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_AND_" *)
module _90_lut_and (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b1000)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_XOR_" *)
module _90_lut_xor (A, B, Y);
input A, B;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
.LUT(4'b0110)
) lut (
.A(AA),
.Y(Y)
);
endmodule
(* techmap_celltype = "$_MUX_" *)
module _90_lut_mux (A, B, S, Y);
input A, B, S;
output Y;
wire [`LUT_WIDTH-1:0] AA;
assign AA = {S, B, A};
\$lut #(
.WIDTH(`LUT_WIDTH),
// A 1010 1010
// B 1100 1100
// S 1111 0000
.LUT(8'b_1100_1010)
) lut (
.A(AA),
.Y(Y)
);
endmodule