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write_xaiger: add support and test for (* keep *) on wires

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This commit is contained in:
Eddie Hung 2020-01-13 19:07:55 -08:00
parent 0d2c06ee47
commit 9ec948f396
2 changed files with 30 additions and 7 deletions
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13
tests/techmap/abc9.ys
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@ -38,3 +38,16 @@ abc9 -lut 4
design -load gold
scratchpad -copy abc9.script.flow3 abc9.script
abc9 -lut 4
design -reset
read_verilog <<EOT
module top(input a, b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 2 t:$lut