From 9ec361beab10941bf70fd2de4a82752c6eae8a11 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 2 Dec 2025 14:03:12 +1300
Subject: [PATCH] test_cell.cc: Generate .aag for all compatible cells

Skips (with warning) on cells that didn't convert to avoid `write_aiger` from raising an error.
---
 passes/tests/test_cell.cc | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 73af155bd..4d28e659b 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -1143,7 +1143,29 @@ struct TestCellPass : public Pass {
 				else
 					uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
 				if (!write_prefix.empty()) {
-					Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
+					string writer = "write_rtlil";
+					string suffix = "il";
+					if (techmap_cmd.compare("aigmap") == 0) {
+						// try to convert to aiger
+						Pass::call(design, techmap_cmd);
+						bool is_unconverted = false;
+						for (auto *mod : design->selected_modules())
+							for (auto *cell : mod->selected_cells())
+								if (!cell->type.in(ID::$_NOT_, ID::$_AND_)) {
+									is_unconverted = true;
+									break;
+								}
+						if (is_unconverted) {
+							// skip unconverted cells
+							log_warning("Skipping %s\n", cell_type);
+							delete design;
+							break;
+						} else {
+							writer = "write_aiger -ascii";
+							suffix = "aag";
+						}
+					}
+					Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix));
 				} else if (edges) {
 					Pass::call(design, "dump gold");
 					run_edges_test(design, verbose);