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design: add test

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This commit is contained in:
Eddie Hung 2020-04-16 12:48:40 -07:00
parent dac5adde12
commit 9eace8f360
2 changed files with 22 additions and 5 deletions
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9
tests/various/design1.ys Normal file
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read_verilog <<EOT
module top(input i, output o);
assign o = i;
endmodule
EOT
design -stash foo
design -delete foo
logger -expect error "No saved design 'foo' found!" 1
design -delete foo