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Towards Xilinx bram support

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This commit is contained in:
Clifford Wolf 2015-01-05 13:59:04 +01:00
parent 8898897f7b
commit 9ea2511fe8
8 changed files with 175 additions and 19 deletions
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36
techlibs/xilinx/synth_xilinx.cc
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@ -69,25 +69,26 @@ struct SynthXilinxPass : public Pass {
log(" hierarchy -check -top <top>\n");
log("\n");
log(" coarse:\n");
log(" proc\n");
log(" opt\n");
log(" memory\n");
log(" clean\n");
log(" fsm\n");
log(" opt\n");
log(" synth -run coarse\n");
log(" memory_bram -rules +/xilinx/brams.txt\n");
log(" techmap -map +/xilinx/brams.v\n");
log("\n");
log(" fine:\n");
log(" techmap\n");
log(" opt\n");
log(" opt -fast -full\n");
log("\n");
log(" map_luts:\n");
log(" abc -lut 6\n");
log(" clean\n");
log("\n");
log(" map_cells:\n");
log(" techmap -share_map xilinx/cells.v\n");
log(" techmap -map +/xilinx/cells.v\n");
log(" clean\n");
log("\n");
log(" flatten:\n");
log(" flatten\n");
log(" opt -fast -full\n");
log("\n");
log(" clkbuf:\n");
log(" select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
log(" iopadmap -inpad BUFGP O:I @xilinx_clocks\n");
@ -163,18 +164,15 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "coarse"))
{
Pass::call(design, "proc");
Pass::call(design, "opt");
Pass::call(design, "memory");
Pass::call(design, "clean");
Pass::call(design, "fsm");
Pass::call(design, "opt");
Pass::call(design, "synth -run coarse");
Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
Pass::call(design, "techmap -map +/xilinx/brams.v");
}
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "techmap");
Pass::call(design, "opt");
Pass::call(design, "opt -fast -full");
}
if (check_label(active, run_from, run_to, "map_luts"))
@ -185,10 +183,16 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, "techmap -share_map xilinx/cells.v");
Pass::call(design, "techmap -map +/xilinx/cells.v");
Pass::call(design, "clean");
}
if (check_label(active, run_from, run_to, "flatten"))
{
Pass::call(design, "flatten");
Pass::call(design, "opt -fast -full");
}
if (check_label(active, run_from, run_to, "clkbuf"))
{
Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str()));