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						9e8a2ac051
					
				
					 1 changed files with 21 additions and 7 deletions
				
			
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					@ -240,13 +240,13 @@ struct IopadmapPass : public Pass {
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		for (auto module : design->selected_modules())
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							for (auto module : design->selected_modules())
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		{
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							{
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			dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
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								dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
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			pool<SigSig> remove_conns;
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								dict<SigSig, pool<int>> remove_conns;
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			if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
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								if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
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			{
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								{
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				dict<SigBit, Cell *> tbuf_bits;
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									dict<SigBit, Cell *> tbuf_bits;
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				pool<SigBit> driven_bits;
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									pool<SigBit> driven_bits;
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				dict<SigBit, SigSig> z_conns;
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									dict<SigBit, std::pair<SigSig, int>> z_conns;
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				// Gather tristate buffers and always-on drivers.
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									// Gather tristate buffers and always-on drivers.
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				for (auto cell : module->cells())
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									for (auto cell : module->cells())
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					@ -266,7 +266,7 @@ struct IopadmapPass : public Pass {
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						SigBit dstbit = conn.first[i];
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											SigBit dstbit = conn.first[i];
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						SigBit srcbit = conn.second[i];
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											SigBit srcbit = conn.second[i];
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						if (!srcbit.wire && srcbit.data == State::Sz) {
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											if (!srcbit.wire && srcbit.data == State::Sz) {
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							z_conns[dstbit] = conn;
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												z_conns[dstbit] = {conn, i};
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							continue;
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												continue;
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						}
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											}
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						driven_bits.insert(dstbit);
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											driven_bits.insert(dstbit);
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					@ -317,8 +317,9 @@ struct IopadmapPass : public Pass {
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							// enable.
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												// enable.
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							en_sig = SigBit(State::S0);
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												en_sig = SigBit(State::S0);
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							data_sig = SigBit(State::Sx);
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												data_sig = SigBit(State::Sx);
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							if (z_conns.count(wire_bit))
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												auto it = z_conns.find(wire_bit);
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								remove_conns.insert(z_conns[wire_bit]);
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												if (it != z_conns.end())
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													remove_conns[it->second.first].insert(it->second.second);
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						}
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											}
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						if (wire->port_input)
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											if (wire->port_input)
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					@ -477,9 +478,22 @@ struct IopadmapPass : public Pass {
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			if (!remove_conns.empty()) {
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								if (!remove_conns.empty()) {
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				std::vector<SigSig> new_conns;
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									std::vector<SigSig> new_conns;
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				for (auto &conn : module->connections())
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									for (auto &conn : module->connections()) {
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					if (!remove_conns.count(conn))
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										auto it = remove_conns.find(conn);
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										if (it == remove_conns.end()) {
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						new_conns.push_back(conn);
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											new_conns.push_back(conn);
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										} else {
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											SigSpec lhs, rhs;
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											for (int i = 0; i < GetSize(conn.first); i++) {
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												if (!it->second.count(i)) {
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													lhs.append(conn.first[i]);
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													rhs.append(conn.second[i]);
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												}
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											}
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											new_conns.push_back(SigSig(lhs, rhs));
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										}
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									}
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				module->new_connections(new_conns);
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									module->new_connections(new_conns);
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			}
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								}
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