mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-12 06:00:55 +00:00
Code Activity

Move $dffe to dffs.{v,ys}

Browse source
This commit is contained in:
Eddie Hung 2019-08-22 12:20:18 -07:00
parent c5754d9e8b
commit 9e537a76b5
4 changed files with 41 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/ice40/dffs.ys
View file

@ -1,11 +1,9 @@
read_verilog dffs.v
proc
flatten
dff2dffe
hierarchy -top top
synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D