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Move $dffe to dffs.{v,ys}

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This commit is contained in:
Eddie Hung 2019-08-22 12:20:18 -07:00
parent c5754d9e8b
commit 9e537a76b5
4 changed files with 41 additions and 18 deletions
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9
tests/ice40/adffs.ys
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@ -1,8 +1,11 @@
read_verilog adffs.v
proc
dff2dffe
synth_ice40
select -assert-count 2 t:SB_DFFR
async2sync
synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_DFFE
select -assert-count 4 t:SB_LUT4
#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D