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Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr

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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
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whitequark 2021-03-05 05:30:19 -08:00 committed by GitHub
parent 06da2e0f18 14ce8bdaa6
commit 9dd813374e
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1 changed files with 3 additions and 1 deletions
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4
backends/cxxrtl/cxxrtl_backend.cc
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@ -1233,7 +1233,9 @@ struct CxxrtlWorker {
RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
std::string valid_index_temp = fresh_temporary(); std::string valid_index_temp = fresh_temporary();
f << indent << "auto " << valid_index_temp << " = memory_index("; f << indent << "auto " << valid_index_temp << " = memory_index(";
dump_sigspec_rhs(cell->getPort(ID::ADDR)); // Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
// memory read ports can.
dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug);
f << ", " << memory->start_offset << ", " << memory->size << ");\n"; f << ", " << memory->start_offset << ", " << memory->size << ");\n";
if (cell->type == ID($memrd)) { if (cell->type == ID($memrd)) {
bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones(); bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();