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Added real->int convertion in ast genrtlil

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This commit is contained in:
Clifford Wolf 2014-06-14 07:44:19 +02:00
parent 7ef0da32cd
commit 9dd16fa41c
1 changed files with 12 additions and 0 deletions
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12
frontends/ast/genrtlil.cc
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@ -602,6 +602,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
sign_hint = false; sign_hint = false;
break; break;
case AST_REALVALUE:
width_hint = std::max(width_hint, 32);
break;
case AST_IDENTIFIER: case AST_IDENTIFIER:
id_ast = id2ast; id_ast = id2ast;
if (id_ast == NULL && current_scope.count(str)) if (id_ast == NULL && current_scope.count(str))
@ -909,6 +913,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return RTLIL::SigSpec(bitsAsConst()); return RTLIL::SigSpec(bitsAsConst());
} }
case AST_REALVALUE:
{
int intvalue = round(realvalue);
log("Warning: converting real value %e to integer %d at %s:%d.\n",
realvalue, intvalue, filename.c_str(), linenum);
return RTLIL::SigSpec(intvalue);
}
// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
// for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
// shifter cell is created and the output signal of this cell is returned // shifter cell is created and the output signal of this cell is returned