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CSA add alumacc related tests.

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nella 2026-03-19 17:45:56 +01:00 • committed by nella
parent 5d90bcc792
commit 9dc408eea7
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tests/csa_tree/csa_tree_macc.ys Normal file
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# Tests for csa_tree operating on $macc cells (post-alumacc)
# After alumacc, chains of adds get merged into a single $macc cell.
# The csa_tree pass should decompose it into FA + final add.
# 3-input add merged into $macc
read_verilog <<EOT
module macc_add3(
input [7:0] a, b, c,
output [7:0] y
);
assign y = a + b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-count 1 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$macc t:$macc_v2 %u
design -reset
# 4-input add merged into $macc
read_verilog <<EOT
module macc_add4(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$macc t:$macc_v2 %u
design -reset
# 5-input add merged into $macc
read_verilog <<EOT
module macc_add5(
input [11:0] a, b, c, d, e,
output [11:0] y
);
assign y = a + b + c + d + e;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$macc t:$macc_v2 %u
design -reset
# 8-input add merged into $macc
read_verilog <<EOT
module macc_add8(
input [15:0] a, b, c, d, e, f, g, h,
output [15:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$macc t:$macc_v2 %u
design -reset
read_verilog <<EOT
module macc_sub_mixed(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b - c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module macc_const(
input [7:0] a, b, c,
output [7:0] y
);
assign y = a + b + c + 8'd42;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module macc_two(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y1, y2
);
assign y1 = a + b + c + d;
assign y2 = e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-count 4 t:$fa
select -assert-count 2 t:$add
design -reset