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efinix: Use memory_libmap pass.
This commit is contained in:
Marcelina Kościelnicka
parent
f4d1426229
commit
9d11575856
4 changed files with 164 additions and 102 deletions
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@ -1,32 +1,19 @@
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bram $__EFINIX_5K
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init 1
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abits 8 @a8d16
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dbits 16 @a8d16
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abits 9 @a9d8
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dbits 8 @a9d8
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abits 10 @a10d4
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dbits 4 @a10d4
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abits 11 @a11d2
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dbits 2 @a11d2
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abits 12 @a12d1
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dbits 1 @a12d1
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abits 8 @a8d20
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dbits 20 @a8d20
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abits 9 @a9d10
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dbits 10 @a9d10
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groups 2
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ports 1 1
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wrmode 1 0
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enable 1 1
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transp 0 2
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clocks 2 3
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clkpol 2 3
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endbram
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match $__EFINIX_5K
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min bits 256
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min efficiency 5
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shuffle_enable B
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endmatch
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ram block $__EFINIX_5K_ {
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abits 12;
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widths 1 2 5 10 20 per_port;
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cost 32;
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init no_undef;
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port sr "R" {
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clock anyedge;
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rden;
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}
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port sw "W" {
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clock anyedge;
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option "WRITE_MODE" "READ_FIRST" {
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wrtrans "R" old;
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}
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option "WRITE_MODE" "WRITE_FIRST" {
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wrtrans "R" new;
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}
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}
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}
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@ -1,65 +1,149 @@
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module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 20;
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parameter CFG_ENABLE_A = 1;
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module $__EFINIX_5K_ (...);
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parameter INIT = 0;
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parameter OPTION_WRITE_MODE = "READ_FIRST";
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [5119:0] INIT = 5119'bx;
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parameter TRANSP2 = 0;
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parameter PORT_R_WIDTH = 20;
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parameter PORT_R_CLK_POL = 1;
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parameter PORT_W_WIDTH = 20;
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parameter PORT_W_CLK_POL = 1;
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input CLK2;
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input CLK3;
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input PORT_R_CLK;
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input PORT_R_RD_EN;
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input [11:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input PORT_W_CLK;
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input PORT_W_WR_EN;
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input [11:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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localparam IS_5BIT = PORT_R_WIDTH >= 5 && PORT_W_WIDTH >= 5;
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localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
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localparam RADDR_WIDTH =
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PORT_R_WIDTH == 1 ? 12 :
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PORT_R_WIDTH == 2 ? 11 :
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PORT_R_WIDTH == 5 ? 10 :
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PORT_R_WIDTH == 10 ? 9 :
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8;
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localparam WADDR_WIDTH =
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PORT_W_WIDTH == 1 ? 12 :
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PORT_W_WIDTH == 2 ? 11 :
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PORT_W_WIDTH == 5 ? 10 :
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PORT_W_WIDTH == 10 ? 9 :
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8;
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localparam READ_WIDTH =
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PORT_R_WIDTH == 1 ? 1 :
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PORT_R_WIDTH == 2 ? 2 :
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PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
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PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
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(IS_5BIT ? 20 : 16);
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localparam WRITE_WIDTH =
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PORT_W_WIDTH == 1 ? 1 :
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PORT_W_WIDTH == 2 ? 2 :
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PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
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PORT_W_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
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(IS_5BIT ? 20 : 16);
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wire [RADDR_WIDTH-1:0] RADDR = PORT_R_ADDR[11:12-RADDR_WIDTH];
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wire [WADDR_WIDTH-1:0] WADDR = PORT_W_ADDR[11:12-WADDR_WIDTH];
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wire [WRITE_WIDTH-1:0] WDATA;
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wire [READ_WIDTH-1:0] RDATA;
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generate
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case (WRITE_WIDTH)
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1: assign WDATA = PORT_W_WR_DATA;
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2: assign WDATA = PORT_W_WR_DATA;
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4: assign WDATA = PORT_W_WR_DATA[3:0];
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5: assign WDATA = PORT_W_WR_DATA;
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8: assign WDATA = {
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PORT_W_WR_DATA[8:5],
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PORT_W_WR_DATA[3:0]
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};
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10: assign WDATA = PORT_W_WR_DATA;
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16: assign WDATA = {
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PORT_W_WR_DATA[18:15],
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PORT_W_WR_DATA[13:10],
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PORT_W_WR_DATA[8:5],
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PORT_W_WR_DATA[3:0]
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};
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20: assign WDATA = PORT_W_WR_DATA;
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endcase
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case (READ_WIDTH)
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1: assign PORT_R_RD_DATA = RDATA;
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2: assign PORT_R_RD_DATA = RDATA;
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4: assign PORT_R_RD_DATA[3:0] = RDATA;
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5: assign PORT_R_RD_DATA = RDATA;
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8: assign {
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PORT_R_RD_DATA[8:5],
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PORT_R_RD_DATA[3:0]
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} = RDATA;
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10: assign PORT_R_RD_DATA = RDATA;
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16: assign {
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PORT_R_RD_DATA[18:15],
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PORT_R_RD_DATA[13:10],
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PORT_R_RD_DATA[8:5],
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PORT_R_RD_DATA[3:0]
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} = RDATA;
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20: assign PORT_R_RD_DATA = RDATA;
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endcase
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endgenerate
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function [255:0] init_slice;
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input integer idx;
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integer i;
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if (IS_5BIT)
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init_slice = INIT[idx * 256 +: 256];
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else if (idx > 16)
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init_slice = 0;
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else
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for (i = 0; i < 64; i = i + 1)
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init_slice[i*4+:4] = INIT[(idx * 64 + i) * 5+:4];
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endfunction
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EFX_RAM_5K #(
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.READ_WIDTH(CFG_DBITS),
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.WRITE_WIDTH(CFG_DBITS),
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.OUTPUT_REG(1'b0),
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.RCLK_POLARITY(1'b1),
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.RE_POLARITY(1'b1),
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.WCLK_POLARITY(1'b1),
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.WE_POLARITY(1'b1),
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.WCLKE_POLARITY(1'b1),
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.WRITE_MODE(WRITEMODE_A),
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.INIT_0(INIT[ 0*256 +: 256]),
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.INIT_1(INIT[ 1*256 +: 256]),
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.INIT_2(INIT[ 2*256 +: 256]),
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.INIT_3(INIT[ 3*256 +: 256]),
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.INIT_4(INIT[ 4*256 +: 256]),
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.INIT_5(INIT[ 5*256 +: 256]),
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.INIT_6(INIT[ 6*256 +: 256]),
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.INIT_7(INIT[ 7*256 +: 256]),
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.INIT_8(INIT[ 8*256 +: 256]),
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.INIT_9(INIT[ 9*256 +: 256]),
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.INIT_A(INIT[10*256 +: 256]),
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.INIT_B(INIT[11*256 +: 256]),
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.INIT_C(INIT[12*256 +: 256]),
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.INIT_D(INIT[13*256 +: 256]),
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.INIT_E(INIT[14*256 +: 256]),
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.INIT_F(INIT[15*256 +: 256]),
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.INIT_10(INIT[16*256 +: 256]),
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.INIT_11(INIT[17*256 +: 256]),
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.INIT_12(INIT[18*256 +: 256]),
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.INIT_13(INIT[19*256 +: 256])
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.READ_WIDTH(READ_WIDTH),
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.WRITE_WIDTH(WRITE_WIDTH),
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.OUTPUT_REG(1'b0),
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.RCLK_POLARITY(PORT_R_CLK_POL),
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.RE_POLARITY(1'b1),
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.WCLK_POLARITY(PORT_W_CLK_POL),
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.WE_POLARITY(1'b1),
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.WCLKE_POLARITY(1'b1),
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.WRITE_MODE(OPTION_WRITE_MODE),
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.INIT_0(init_slice('h00)),
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.INIT_1(init_slice('h01)),
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.INIT_2(init_slice('h02)),
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.INIT_3(init_slice('h03)),
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.INIT_4(init_slice('h04)),
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.INIT_5(init_slice('h05)),
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.INIT_6(init_slice('h06)),
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.INIT_7(init_slice('h07)),
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.INIT_8(init_slice('h08)),
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.INIT_9(init_slice('h09)),
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.INIT_A(init_slice('h0a)),
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.INIT_B(init_slice('h0b)),
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.INIT_C(init_slice('h0c)),
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.INIT_D(init_slice('h0d)),
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.INIT_E(init_slice('h0e)),
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.INIT_F(init_slice('h0f)),
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.INIT_10(init_slice('h10)),
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.INIT_11(init_slice('h11)),
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.INIT_12(init_slice('h12)),
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.INIT_13(init_slice('h13)),
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) _TECHMAP_REPLACE_ (
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.WDATA(A1DATA),
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.WADDR(A1ADDR),
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.WE(A1EN),
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.WCLK(CLK2),
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.WCLKE(1'b1),
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.RDATA(B1DATA),
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.RADDR(B1ADDR),
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.RE(B1EN),
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.RCLK(CLK3)
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.WDATA(WDATA),
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.WADDR(WADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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.WCLKE(1'b1),
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.RDATA(RDATA),
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.RADDR(RADDR),
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.RE(PORT_R_RD_EN),
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.RCLK(PORT_R_CLK)
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);
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endmodule
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@ -158,11 +158,13 @@ struct SynthEfinixPass : public ScriptPass
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run("synth -run coarse");
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}
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if (!nobram || check_label("map_bram", "(skip if -nobram)"))
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if (check_label("map_ram"))
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{
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run("memory_bram -rules +/efinix/brams.txt");
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std::string args = "";
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if (nobram)
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args += " -no-auto-block";
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run("memory_libmap -lib +/efinix/brams.txt" + args);
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run("techmap -map +/efinix/brams_map.v");
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run("setundef -zero -params t:EFX_RAM_5K");
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}
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if (check_label("map_ffram"))
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@ -1,17 +1,6 @@
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Called with -verify and proof did fail!
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#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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synth_efinix
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cd lutram_1w1r
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_RAM_5K
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