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add dsp inference
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parent
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commit
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12 changed files with 7189 additions and 7 deletions
50
techlibs/quicklogic/ql_dsp_macc.pmg
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50
techlibs/quicklogic/ql_dsp_macc.pmg
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@ -0,0 +1,50 @@
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pattern ql_dsp_macc
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state <IdString> add_ba
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state <IdString> mux_ab
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state <int> mul_nusers
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state <int> add_nusers
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state <int> mux_nusers
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state <int> ff_d_nusers
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state <int> ff_q_nusers
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match mul
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select mul->type.in($mul)
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select nusers(port(mul, \Y)) <= 3
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set mul_nusers nusers(port(mul, \Y))
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endmatch
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match add
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select add->type.in($add, $sub)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(add, AB) === port(mul, \Y)
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select nusers(port(add, \Y)) <= 3
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set add_nusers nusers(port(add, \Y))
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set add_ba BA
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endmatch
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match mux
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select mux->type.in($mux)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, AB) === port(mul, \Y)
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index <SigSpec> port(mux, BA) === port(add, \Y)
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select nusers(port(mux, \Y)) <= 3
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set mux_nusers nusers(port(mux, \Y))
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set mux_ab AB
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optional
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endmatch
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match ff
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select ff->type.in($dff, $adff, $dffe, $adffe)
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index <SigSpec> port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y))
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index <SigSpec> port(ff, \Q) === port(add, add_ba)
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set ff_d_nusers nusers(port(ff, \D))
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set ff_q_nusers nusers(port(ff, \Q))
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endmatch
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code
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accept;
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endcode
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