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https://github.com/YosysHQ/yosys
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add dsp inference
This commit is contained in:
N. Engelhardt
Martin Povišer
parent
7c0dbc8822
commit
9ce53ea3e2
12 changed files with 7189 additions and 7 deletions
307
techlibs/quicklogic/ql_dsp_macc.cc
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307
techlibs/quicklogic/ql_dsp_macc.cc
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/*
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* Copyright 2020-2022 F4PGA Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "ql_dsp_macc_pm.h"
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// ============================================================================
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bool use_dsp_cfg_params;
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
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{
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auto &st = pm.st_ql_dsp_macc;
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// Reject if multiplier drives anything else than either $add or $add and
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// $mux
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if (st.mux == nullptr && st.mul_nusers > 2) {
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return;
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}
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// Determine whether the output is taken from before or after the ff
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bool out_ff;
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if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) {
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out_ff = true;
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} else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) {
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out_ff = false;
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} else {
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// Illegal, cannot take the two outputs simulataneously
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return;
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}
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// No mux, the adder can driver either the ff or the ff + output
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if (st.mux == nullptr) {
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if (out_ff && st.add_nusers != 2) {
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return;
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}
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if (!out_ff && st.add_nusers != 3) {
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return;
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}
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}
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// Mux present, the adder cannot drive anything else
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else {
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if (st.add_nusers != 2) {
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return;
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}
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}
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// Mux can driver either the ff or the ff + output
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if (st.mux != nullptr) {
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if (out_ff && st.mux_nusers != 2) {
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return;
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}
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if (!out_ff && st.mux_nusers != 3) {
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return;
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}
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}
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// Accept only posedge clocked FFs
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if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) {
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return;
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}
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// Get port widths
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size_t a_width = GetSize(st.mul->getPort(ID(A)));
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size_t b_width = GetSize(st.mul->getPort(ID(B)));
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size_t z_width = GetSize(st.ff->getPort(ID(Q)));
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size_t min_width = std::min(a_width, b_width);
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size_t max_width = std::max(a_width, b_width);
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// Signed / unsigned
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bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool();
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bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool();
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// Determine DSP type or discard if too narrow / wide
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RTLIL::IdString type;
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size_t tgt_a_width;
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size_t tgt_b_width;
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size_t tgt_z_width;
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string cell_base_name = "dsp_t1";
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string cell_size_name = "";
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string cell_cfg_name = "";
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string cell_full_name = "";
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if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
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// Too narrow
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return;
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} else if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
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cell_size_name = "_10x9x32";
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tgt_a_width = 10;
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tgt_b_width = 9;
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tgt_z_width = 19;
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} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
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cell_size_name = "_20x18x64";
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_z_width = 38;
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} else {
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// Too wide
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return;
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}
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if (use_dsp_cfg_params)
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cell_cfg_name = "_cfg_params";
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else
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cell_cfg_name = "_cfg_ports";
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cell_full_name = cell_base_name + cell_size_name + cell_cfg_name;
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type = RTLIL::escape_id(cell_full_name);
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log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str());
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for (auto cell : {st.mul, st.add, st.mux, st.ff}) {
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if (cell != nullptr) {
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log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str());
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}
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}
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// Build the DSP cell name
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std::string name;
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name += RTLIL::unescape_id(st.mul->name) + "_";
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name += RTLIL::unescape_id(st.add->name) + "_";
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if (st.mux != nullptr) {
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name += RTLIL::unescape_id(st.mux->name) + "_";
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}
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name += RTLIL::unescape_id(st.ff->name);
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// Add the DSP cell
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RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type);
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// Set attributes
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cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true);
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// Get input/output data signals
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RTLIL::SigSpec sig_a;
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RTLIL::SigSpec sig_b;
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RTLIL::SigSpec sig_z;
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if (a_width >= b_width) {
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sig_a = st.mul->getPort(ID(A));
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sig_b = st.mul->getPort(ID(B));
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} else {
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sig_a = st.mul->getPort(ID(B));
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sig_b = st.mul->getPort(ID(A));
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}
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sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
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// Connect input data ports, sign extend / pad with zeros
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sig_a.extend_u0(tgt_a_width, a_signed);
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sig_b.extend_u0(tgt_b_width, b_signed);
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cell->setPort(RTLIL::escape_id("a_i"), sig_a);
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cell->setPort(RTLIL::escape_id("b_i"), sig_b);
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// Connect output data port, pad if needed
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if ((size_t)GetSize(sig_z) < tgt_z_width) {
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auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
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sig_z.append(wire);
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}
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cell->setPort(RTLIL::escape_id("z_o"), sig_z);
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// Connect clock, reset and enable
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cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK)));
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RTLIL::SigSpec rst;
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RTLIL::SigSpec ena;
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if (st.ff->hasPort(ID(ARST))) {
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if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
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rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
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} else {
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rst = st.ff->getPort(ID(ARST));
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}
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} else {
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rst = RTLIL::SigSpec(RTLIL::S0);
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}
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if (st.ff->hasPort(ID(EN))) {
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if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
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ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
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} else {
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ena = st.ff->getPort(ID(EN));
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}
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} else {
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ena = RTLIL::SigSpec(RTLIL::S1);
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}
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cell->setPort(RTLIL::escape_id("reset_i"), rst);
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cell->setPort(RTLIL::escape_id("load_acc_i"), ena);
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// Insert feedback_i control logic used for clearing / loading the accumulator
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if (st.mux != nullptr) {
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RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
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// Depending on the mux port ordering insert inverter if needed
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log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B));
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if (st.mux_ab == ID(A)) {
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sig_s = pm.module->Not(NEW_ID, sig_s);
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}
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// Assemble the full control signal for the feedback_i port
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RTLIL::SigSpec sig_f;
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sig_f.append(sig_s);
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sig_f.append(RTLIL::S0);
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sig_f.append(RTLIL::S0);
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cell->setPort(RTLIL::escape_id("feedback_i"), sig_f);
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}
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// No acc clear/load
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else {
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cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3));
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}
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// Connect control ports
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cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1));
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cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1));
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// Connect config bits
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if (use_dsp_cfg_params) {
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cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0));
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cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6));
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cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0));
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cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0));
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// 3 - output post acc; 1 - output pre acc
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cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
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} else {
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cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6));
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cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0));
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// 3 - output post acc; 1 - output pre acc
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cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3));
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}
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bool subtract = (st.add->type == RTLIL::escape_id("$sub"));
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cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
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// Mark the cells for removal
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pm.autoremove(st.mul);
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pm.autoremove(st.add);
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if (st.mux != nullptr) {
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pm.autoremove(st.mux);
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}
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pm.autoremove(st.ff);
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}
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struct QlDspMacc : public Pass {
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QlDspMacc() : Pass("ql_dsp_macc", "Does something") {}
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void help() override
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{
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log("\n");
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log(" ql_dsp_macc [options] [selection]\n");
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log("\n");
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log(" -use_dsp_cfg_params\n");
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log(" By default use DSP blocks with configuration bits available at module ports.\n");
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log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n");
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log("\n");
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}
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void clear_flags() override { use_dsp_cfg_params = false; }
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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{
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log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < a_Args.size(); argidx++) {
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if (a_Args[argidx] == "-use_dsp_cfg_params") {
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use_dsp_cfg_params = true;
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continue;
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}
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break;
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}
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extra_args(a_Args, argidx, a_Design);
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for (auto module : a_Design->selected_modules()) {
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
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}
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}
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} QlDspMacc;
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PRIVATE_NAMESPACE_END
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