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https://github.com/YosysHQ/yosys
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add dsp inference
This commit is contained in:
N. Engelhardt
Martin Povišer
parent
7c0dbc8822
commit
9ce53ea3e2
12 changed files with 7189 additions and 7 deletions
244
techlibs/quicklogic/ql_dsp_io_regs.cc
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244
techlibs/quicklogic/ql_dsp_io_regs.cc
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/*
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* Copyright 2020-2022 F4PGA Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#define MODE_BITS_REGISTER_INPUTS_ID 92
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#define MODE_BITS_OUTPUT_SELECT_START_ID 81
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#define MODE_BITS_OUTPUT_SELECT_WIDTH 3
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// ============================================================================
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struct QlDspIORegs : public Pass {
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const std::vector<std::string> ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"};
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const std::vector<std::string> ports2del_mult_acc = {"acc_fir", "dly_b"};
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const std::vector<std::string> ports2del_mult_add = {"dly_b"};
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const std::vector<std::string> ports2del_extension = {"saturate_enable", "shift_right", "round"};
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/// Temporary SigBit to SigBit helper map.
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SigMap m_SigMap;
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// ..........................................
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QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {}
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void help() override
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{
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log("\n");
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log(" ql_dsp_io_regs [options] [selection]\n");
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log("\n");
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log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n");
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log("on their configuration.\n");
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}
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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{
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log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < a_Args.size(); argidx++) {
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break;
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}
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extra_args(a_Args, argidx, a_Design);
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for (auto module : a_Design->selected_modules()) {
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ql_dsp_io_regs_pass(module);
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}
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}
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// Returns a pair of mask and value describing constant bit connections of
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// a SigSpec
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std::pair<uint32_t, uint32_t> get_constant_mask_value(const RTLIL::SigSpec *sigspec)
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{
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uint32_t mask = 0L;
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uint32_t value = 0L;
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auto sigbits = sigspec->bits();
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for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) {
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auto other = m_SigMap(sigbits[i]);
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mask <<= 1;
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value <<= 1;
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// A known constant
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if (!other.is_wire() && other.data != RTLIL::Sx) {
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mask |= 0x1;
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value |= (other.data == RTLIL::S1);
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}
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}
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return std::make_pair(mask, value);
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}
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void ql_dsp_io_regs_pass(RTLIL::Module *module)
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{
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// Setup the SigMap
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m_SigMap.clear();
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m_SigMap.set(module);
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for (auto cell : module->cells_) {
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std::string cell_type = cell.second->type.str();
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if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) {
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auto dsp = cell.second;
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// If the cell does not have the "is_inferred" attribute set
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// then don't touch it.
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if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) {
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continue;
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}
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bool del_clk = true;
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bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3"));
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int reg_in_i;
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int out_sel_i;
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// Get DSP configuration
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if (use_dsp_cfg_params) {
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// Read MODE_BITS at correct indexes
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auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS"));
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RTLIL::Const register_inputs;
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register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID);
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reg_in_i = register_inputs.as_int();
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RTLIL::Const output_select;
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output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH);
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out_sel_i = output_select.as_int();
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} else {
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// Read dedicated configuration ports
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const RTLIL::SigSpec *register_inputs;
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register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs"));
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if (!register_inputs)
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log_error("register_inputs port not found!");
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auto reg_in_c = register_inputs->as_const();
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reg_in_i = reg_in_c.as_int();
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const RTLIL::SigSpec *output_select;
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output_select = &dsp->getPort(RTLIL::escape_id("output_select"));
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if (!output_select)
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log_error("output_select port not found!");
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auto out_sel_c = output_select->as_const();
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out_sel_i = out_sel_c.as_int();
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}
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// Get the feedback port
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const RTLIL::SigSpec *feedback;
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feedback = &dsp->getPort(RTLIL::escape_id("feedback"));
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if (!feedback)
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log_error("feedback port not found!");
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// Check if feedback is or can be set to 0 which implies MACC
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auto feedback_con = get_constant_mask_value(feedback);
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bool have_macc = (feedback_con.second == 0x0);
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// log("mask=0x%08X value=0x%08X\n", consts.first, consts.second);
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// log_error("=== END HERE ===\n");
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// Build new type name
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std::string new_type = cell_type;
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new_type += "_MULT";
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if (have_macc) {
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switch (out_sel_i) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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del_clk = false;
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new_type += "ACC";
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break;
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default:
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break;
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}
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} else {
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switch (out_sel_i) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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new_type += "ADD";
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break;
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default:
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break;
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}
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}
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if (reg_in_i) {
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del_clk = false;
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new_type += "_REGIN";
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}
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if (out_sel_i > 3) {
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del_clk = false;
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new_type += "_REGOUT";
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}
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// Set new type name
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dsp->type = RTLIL::IdString(new_type);
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std::vector<std::string> ports2del;
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if (del_clk)
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ports2del.push_back("clk");
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switch (out_sel_i) {
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case 0:
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case 4:
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case 6:
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ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end());
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// Mark for deleton additional configuration ports
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if (!use_dsp_cfg_params) {
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ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end());
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}
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break;
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case 1:
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case 2:
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case 3:
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case 5:
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case 7:
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if (have_macc) {
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ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end());
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} else {
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ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end());
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}
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break;
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}
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for (auto portname : ports2del) {
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const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname));
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if (!port)
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log_error("%s port not found!", portname.c_str());
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dsp->connections_.erase(RTLIL::escape_id(portname));
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}
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}
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}
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// Clear the sigmap
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m_SigMap.clear();
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}
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} QlDspIORegs;
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PRIVATE_NAMESPACE_END
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