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Towards Xilinx bram support

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This commit is contained in:
Clifford Wolf 2015-01-06 13:33:51 +01:00
parent 462b22f44f
commit 9c7f47bbd5
3 changed files with 10 additions and 6 deletions
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8
techlibs/xilinx/tests/bram1_tb.v
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@ -40,10 +40,13 @@ module bram1_tb #(
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd;
event error;
reg error_ind = 0;
integer i, j;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, bram1_tb);
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
clk <= 0;
for (i = 0; i < 256; i = i+1) begin
WR_DATA <= i;
@ -68,6 +71,7 @@ module bram1_tb #(
end
$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
end
end
endmodule