mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 03:45:52 +00:00
Code Activity

Towards Xilinx bram support

Browse source
This commit is contained in:
Clifford Wolf 2015-01-06 13:33:51 +01:00
parent 462b22f44f
commit 9c7f47bbd5
3 changed files with 10 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/brams.v
View file

@ -13,8 +13,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
input [71:0] B1DATA;
input [7:0] B1EN;
wire [15:0] A1ADDR_16 = A1ADDR;
wire [15:0] B1ADDR_16 = B1ADDR;
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
wire [7:0] DIP, DOP;
wire [63:0] DI, DO;