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https://github.com/YosysHQ/yosys
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Merge 0b1f45097a
into 733487e730
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commit
9c571fbdd2
1 changed files with 46 additions and 0 deletions
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@ -19,6 +19,8 @@
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#include "kernel/yosys.h"
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#include "kernel/yosys.h"
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#include "kernel/macc.h"
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#include "kernel/macc.h"
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#include "kernel/utils.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/celltypes.h"
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#include "kernel/binding.h"
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#include "kernel/binding.h"
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#include "kernel/sigtools.h"
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#include "kernel/sigtools.h"
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@ -2208,6 +2210,47 @@ namespace {
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}
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}
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#endif
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#endif
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static void sort_cells_topologically(RTLIL::Module * module)
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{
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CellTypes ct_combinational;
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ct_combinational.setup_internals();
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ct_combinational.setup_stdcells();
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SigMap assign_map(module);
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->cells()) {
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if (ct_combinational.cell_known(cell->type))
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for (auto &conn : cell->connections()) {
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RTLIL::SigSpec sig = assign_map(conn.second);
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sig.remove_const();
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if (ct_combinational.cell_input(cell->type, conn.first))
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cell_to_inbit[cell].insert(sig.begin(), sig.end());
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if (ct_combinational.cell_output(cell->type, conn.first))
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for (auto &bit : sig)
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outbit_to_cell[bit].insert(cell);
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}
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cells.node(cell);
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}
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for (auto &it_right : cell_to_inbit)
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for (auto &it_sigbit : it_right.second)
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for (auto &it_left : outbit_to_cell[it_sigbit])
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// reverse edge direction so we end up with reverse sorted cell list
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cells.edge(it_right.first, it_left);
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cells.sort();
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dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
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for (auto cell : cells.sorted)
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// dict<> iterator order is reverse insert order
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new_cells[cell->name] = cell;
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new_cells.swap(module->cells_);
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}
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void RTLIL::Module::sort()
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void RTLIL::Module::sort()
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{
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{
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wires_.sort(sort_by_id_str());
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wires_.sort(sort_by_id_str());
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@ -2221,6 +2264,9 @@ void RTLIL::Module::sort()
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it.second->attributes.sort(sort_by_id_str());
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it.second->attributes.sort(sort_by_id_str());
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for (auto &it : memories)
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for (auto &it : memories)
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it.second->attributes.sort(sort_by_id_str());
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it.second->attributes.sort(sort_by_id_str());
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if (design->scratchpad_get_bool("toposort_cells", true))
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sort_cells_topologically(this);
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}
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}
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void RTLIL::Module::check()
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void RTLIL::Module::check()
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