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Add test

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This commit is contained in:
Eddie Hung 2019-07-02 19:13:40 -07:00
parent 0447794c51
commit 9c556e3c02
2 changed files with 14 additions and 0 deletions
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4
tests/various/abc9.v
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@ -3,3 +3,7 @@ initial o = 1'b0;
always @* always @*
o <= ~o; o <= ~o;
endmodule endmodule
module abc9_test028(input i, output o);
unknown u(~i, o);
endmodule

10
tests/various/abc9.ys
View file

@ -1,4 +1,6 @@
read_verilog abc9.v read_verilog abc9.v
design -save read
hierarchy -top abc9_test027
proc proc
design -save gold design -save gold
@ -12,3 +14,11 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top abc9_test028
proc
abc9 -lut 4
select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D