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Progress in presentation
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@ -239,6 +239,51 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
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\subsectionpagesuffix
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\end{frame}
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\subsubsection{Introduction to techmap}
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\begin{frame}{\subsubsecname}
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\begin{itemize}
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\item
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The {\tt techmap} command replaces cells in the design with implementations given
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as verilog code (called ``map files''). It can replace Yosys' internal cell
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types (such as {\tt \$or}) as well as user-defined cell types.
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\medskip\item
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Verilog parameters are used extensively to customize the internal cell types.
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\medskip\item
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Additional special parameters are used by techmap to communicate meta-data to the
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map files.
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\medskip\item
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Special wires are used to instruct techmap how to handle a module in the map file.
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\medskip\item
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Generate blocks and recursion are powerful tools for writing map files.
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\end{itemize}
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\end{frame}
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\begin{frame}[t]{\subsubsecname -- Example 1/2}
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\vskip-0.2cm
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To map the Verilog OR-reduction operator to 3-input OR gates:
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\vskip-0.2cm
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\begin{columns}
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\column[t]{0.35\linewidth}
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\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
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\column[t]{0.65\linewidth}
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\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
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\end{columns}
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\end{frame}
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\begin{frame}[t]{\subsubsecname -- Example 2/2}
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\vbox to 0cm{
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\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
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\vss
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}
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\begin{columns}
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\column[t]{6cm}
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\column[t]{4cm}
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\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
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\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
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\end{columns}
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\end{frame}
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\subsubsection{TBD}
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\begin{frame}{\subsubsecname}
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