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Progress in presentation

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Clifford Wolf 2014-02-16 13:45:47 +01:00
parent 7ac524e8e8
commit 9c29969bbc
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manual/PRESENTATION_ExAdv/red_or3x1_test.ys Normal file
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read_verilog red_or3x1_test.v
hierarchy -check -top test
techmap -map red_or3x1_map.v;;
splitnets -ports
show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v