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Progress in presentation

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Clifford Wolf 2014-02-16 13:45:47 +01:00
parent 7ac524e8e8
commit 9c29969bbc
6 changed files with 114 additions and 1 deletions
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5
manual/PRESENTATION_ExAdv/Makefile
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all: select_01.pdf
all: select_01.pdf red_or3x1.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys

5
manual/PRESENTATION_ExAdv/red_or3x1_cells.v Normal file
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module OR3X1(A, B, C, Y);
input A, B, C;
output Y;
assign Y = A | B | C;
endmodule

48
manual/PRESENTATION_ExAdv/red_or3x1_map.v Normal file
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module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
function integer min;
input integer a, b;
begin
if (a < b)
min = a;
else
min = b;
end
endfunction
genvar i;
generate begin
if (A_WIDTH == 0) begin
assign Y = 0;
end
if (A_WIDTH == 1) begin
assign Y = A;
end
if (A_WIDTH == 2) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH == 3) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH > 3) begin
localparam next_stage_sz = (A_WIDTH+2) / 3;
wire [next_stage_sz-1:0] next_stage;
for (i = 0; i < next_stage_sz; i = i+1) begin
localparam bits = min(A_WIDTH - 3*i, 3);
assign next_stage[i] = |A[3*i +: bits];
end
assign Y = |next_stage;
end
end endgenerate
endmodule

5
manual/PRESENTATION_ExAdv/red_or3x1_test.v Normal file
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module test (A, Y);
input [6:0] A;
output Y;
assign Y = |A;
endmodule

7
manual/PRESENTATION_ExAdv/red_or3x1_test.ys Normal file
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read_verilog red_or3x1_test.v
hierarchy -check -top test
techmap -map red_or3x1_map.v;;
splitnets -ports
show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v