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Remove DSP48E1 from *_cells_xtra.v

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This commit is contained in:
Eddie Hung 2019-10-04 17:26:42 -07:00
parent 74ef8feeaf
commit 9c23811839
3 changed files with 2 additions and 178 deletions
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4
techlibs/xilinx/cells_xtra.py
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@ -137,7 +137,7 @@ XC6V_CELLS = [
Cell('SYSMON'),
# Arithmetic functions.
Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
# Clock components.
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
@ -264,7 +264,7 @@ XC7_CELLS = [
Cell('XADC'),
# Arithmetic functions.
Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
# Clock components.
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),