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Typos and grammar fixes through chapter 2.

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Anthony J. Bentley 2014-04-11 02:42:59 -06:00
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manual/manual.tex
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@ -140,7 +140,7 @@ bookmarksopen=false%
\eject
\chapter*{Abstract}
Most of todays digital design is done in HDL code (mostly Verilog or VHDL) and
Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries or when
@ -158,7 +158,7 @@ by Yosys to perform advanced gate-level optimizations.
An evaluation of Yosys based on real-world designs is included. It is shown
that Yosys can be used as-is to synthesize such designs. The results produced
by Yosys in this tests where successflly verified using formal verification
and are compareable in quality to the results produced by a commercial
and are comparable in quality to the results produced by a commercial
synthesis tool.
\bigskip