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Revert PRs #2203 and #2244.

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This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
This commit is contained in:
whitequark 2020-07-09 18:13:04 +00:00
parent f313211c32
commit 9c120b89ac
5 changed files with 10 additions and 68 deletions
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6
tests/various/integer_range_bad_syntax.ys
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@ -1,6 +0,0 @@
logger -expect error "syntax error, unexpected" 1
read_verilog -sv <<EOT
module test_integer_range();
parameter integer [31:0] a = 0;
endmodule
EOT

6
tests/various/integer_real_bad_syntax.ys
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@ -1,6 +0,0 @@
logger -expect error "syntax error, unexpected TOK_REAL" 1
read_verilog -sv <<EOT
module test_integer_real();
parameter integer real a = 0;
endmodule
EOT

9
tests/various/logic_param_simple.ys
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@ -1,9 +0,0 @@
read_verilog -sv <<EOT
module test_logic_param();
parameter logic a = 0;
parameter logic [31:0] e = 0;
parameter logic signed b = 0;
parameter logic unsigned c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT

28
tests/various/signed.ys
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@ -1,28 +0,0 @@
# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT