Unify verilog style

tests/arch/common/add_sub.v

@@ -5,9 +5,8 @@ module top
 
     output [3:0] A,
     output [3:0] B
- );
+);
-
-assign A =  x + y;
-assign B =  x - y;
 
+    assign A =  x + y;
+    assign B =  x - y;
 endmodule

tests/arch/common/adffs.v

@@ -1,5 +1,4 @@
-module adff
+module adff( input d, clk, clr, output reg q );
-    ( input d, clk, clr, output reg q );
     initial begin
         q = 0;
     end
@@ -10,8 +9,7 @@ module adff
         q <= d;
 endmodule
 
-module adffn
+module adffn( input d, clk, clr, output reg q );
-    ( input d, clk, clr, output reg q );
     initial begin
       q = 0;
     end
@@ -22,8 +20,7 @@ module adffn
         q <= d;
 endmodule
 
-module dffs
+module dffs( input d, clk, pre, clr, output reg q );
-    ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
@@ -34,8 +31,7 @@ module dffs
         q <= d;
 endmodule
 
-module ndffnr
+module ndffnr( input d, clk, pre, clr, output reg q );
-    ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end

tests/arch/common/counter.v

@@ -1,17 +1,11 @@
-module top    (
+module top ( out, clk, reset );
-out,
-clk,
-reset
-);
     output [7:0] out;
     input clk, reset;
     reg [7:0] out;
 
     always @(posedge clk, posedge reset)
-		if (reset) begin
+      if (reset)
-			out <= 8'b0 ;
+          out <= 8'b0;
-		end else
+      end
           out <= out + 1;
-
-
 endmodule

tests/arch/common/dffs.v

@@ -1,11 +1,9 @@
-module dff
+module dff ( input d, clk, output reg q );
-    ( input d, clk, output reg q );
 	  always @( posedge clk )
         q <= d;
 endmodule
 
-module dffe
+module dffe( input d, clk, en, output reg q );
-    ( input d, clk, en, output reg q );
     initial begin
         q = 0;
     end

tests/arch/common/fsm.v

@@ -1,18 +1,14 @@
- module fsm (
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
     input   clock,reset,req_0,req_1;
     output  gnt_0,gnt_1;
     wire    clock,reset,req_0,req_1;
     reg     gnt_0,gnt_1;
 
- parameter SIZE = 3           ;
+    parameter SIZE = 3;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+    parameter IDLE = 3'b001;
+    parameter GNT0 = 3'b010;
+    parameter GNT1 = 3'b100;
+    parameter GNT2 = 3'b101;
 
     reg [SIZE-1:0] state;
     reg [SIZE-1:0] next_state;
@@ -23,7 +19,8 @@
             state <=  #1  IDLE;
             gnt_0 <= 0;
             gnt_1 <= 0;
- end else
+          end 
+          else
             case(state)
               IDLE :  if (req_0 == 1'b1) begin
                           state <=  #1  GNT0;
@@ -51,5 +48,4 @@
               default : state <=  #1  IDLE;
             endcase
         end
-
 endmodule

tests/arch/common/latches.v

@@ -1,19 +1,16 @@
-module latchp
+module latchp ( input d, clk, en, output reg q );
-    ( input d, clk, en, output reg q );
 	always @*
 		if ( en )
 			q <= d;
 endmodule
 
-module latchn
+module latchn ( input d, clk, en, output reg q );
-    ( input d, clk, en, output reg q );
 	always @*
 		if ( !en )
 			q <= d;
 endmodule
 
-module latchsr
+module latchsr ( input d, clk, en, clr, pre, output reg q );
-    ( input d, clk, en, clr, pre, output reg q );
 	always @*
 		if ( clr )
 			q <= 1'b0;

tests/arch/common/logic.v

@@ -2,8 +2,7 @@ module top
 (
     input [0:7] in,
     output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
+);
-
     assign B1 =  in[0] & in[1];
     assign B2 =  in[0] | in[1];
     assign B3 =  in[0] ~& in[1];
@@ -14,5 +13,4 @@ module top
     assign B8 =  in[0];
     assign B9 =  in[0:1] && in [2:3];
     assign B10 =  in[0:1] || in [2:3];
-
 endmodule

tests/arch/common/mul.v

@@ -4,8 +4,6 @@ module top
     input [5:0] y,
 
     output [11:0] A,
- );
+);
-
+    assign A =  x * y;
-assign A =  x * y;
-
 endmodule

tests/arch/common/mux.v

@@ -8,39 +8,36 @@ module mux2 (S,A,B,Y);
 endmodule
 
 module mux4 ( S, D, Y );
+    input[1:0] S;
+    input[3:0] D;
+    output Y;
 
-input[1:0] S;
+    reg Y;
-input[3:0] D;
+    wire[1:0] S;
-output Y;
+    wire[3:0] D;
 
-reg Y;
+    always @*
-wire[1:0] S;
+    begin
-wire[3:0] D;
-
-always @*
-begin
         case( S )
             0 : Y = D[0];
             1 : Y = D[1];
             2 : Y = D[2];
             3 : Y = D[3];
         endcase
-end
+    end
-
 endmodule
 
 module mux8 ( S, D, Y );
+    input[2:0] S;
+    input[7:0] D;
+    output Y;
 
-input[2:0] S;
+    reg Y;
-input[7:0] D;
+    wire[2:0] S;
-output Y;
+    wire[7:0] D;
 
-reg Y;
+    always @*
-wire[2:0] S;
+    begin
-wire[7:0] D;
-
-always @*
-begin
         case( S )
             0 : Y = D[0];
             1 : Y = D[1];
@@ -51,8 +48,7 @@ begin
             6 : Y = D[6];
             7 : Y = D[7];
         endcase
-end
+    end
-
 endmodule
 
 module mux16 (D, S, Y);
@@ -60,6 +56,5 @@ module mux16 (D, S, Y);
  	input  [3:0] S;
  	output Y;
 
-assign Y = D[S];
+    assign Y = D[S];
-
 endmodule

tests/arch/common/shifter.v

@@ -1,8 +1,4 @@
-module top    (
+module top(out, clk, in);
-out,
-clk,
-in
-);
     output [7:0] out;
     input signed clk, in;
     reg signed [7:0] out = 0;
@@ -12,5 +8,4 @@ in
 		out    <= out >> 1;
 		out[7] <= in;
 	end    
-
 endmodule

tests/arch/common/tribuf.v

@@ -1,4 +1,4 @@
-module tristate (en, i, o);
+module tristate(en, i, o);
     input en;
     input i;
     output reg o;