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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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6
tests/arch/common/tribuf.v
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@ -1,8 +1,8 @@
module tristate (en, i, o);
module tristate(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
o <= (en)? i : 1'bZ;
endmodule