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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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9
tests/arch/common/shifter.v
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@ -1,8 +1,4 @@
module top (
out,
clk,
in
);
module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
@ -11,6 +7,5 @@ in
begin
out <= out >> 1;
out[7] <= in;
end
end
endmodule