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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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9
tests/arch/common/latches.v
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@ -1,19 +1,16 @@
module latchp
( input d, clk, en, output reg q );
module latchp ( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
module latchn
( input d, clk, en, output reg q );
module latchn ( input d, clk, en, output reg q );
always @*
if ( !en )
q <= d;
endmodule
module latchsr
( input d, clk, en, clr, pre, output reg q );
module latchsr ( input d, clk, en, clr, pre, output reg q );
always @*
if ( clr )
q <= 1'b0;