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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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18
tests/arch/common/dffs.v
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@ -1,15 +1,13 @@
module dff
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
module dff ( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
module dffe( input d, clk, en, output reg q );
initial begin
q = 0;
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
always @( posedge clk )
if ( en )
q <= d;
endmodule