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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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16
tests/arch/common/counter.v
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@ -1,17 +1,11 @@
module top (
out,
clk,
reset
);
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
if (reset)
out <= 8'b0;
end
out <= out + 1;
endmodule