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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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54
tests/arch/common/adffs.v
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@ -1,47 +1,43 @@
module adff
( input d, clk, clr, output reg q );
module adff( input d, clk, clr, output reg q );
initial begin
q = 0;
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
module adffn( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffs
( input d, clk, pre, clr, output reg q );
module dffs( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( pre )
q <= 1'b1;
else
q <= d;
always @( posedge clk )
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnr
( input d, clk, pre, clr, output reg q );
module ndffnr( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk )
if ( !clr )
q <= 1'b0;
else
q <= d;
always @( negedge clk )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule