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Unify verilog style

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:50:24 +02:00
parent 12383f37b2
commit 9bd9db56c8
11 changed files with 153 additions and 187 deletions
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15
tests/arch/common/add_sub.v
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@ -1,13 +1,12 @@
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule