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	Merge pull request #2626 from zachjs/param-no-default
sv: support for parameters without default values
This commit is contained in:
		
						commit
						9bb839c613
					
				
					 12 changed files with 225 additions and 5 deletions
				
			
		
							
								
								
									
										17
									
								
								tests/verilog/localparam_no_default_1.ys
									
										
									
									
									
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										17
									
								
								tests/verilog/localparam_no_default_1.ys
									
										
									
									
									
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			@ -0,0 +1,17 @@
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logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module #(
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    localparam X = 1
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);
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endmodule
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EOF
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design -reset
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logger -expect error "localparam initialization is missing!" 1
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read_verilog <<EOF
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module Module #(
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    localparam X
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);
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endmodule
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EOF
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										15
									
								
								tests/verilog/localparam_no_default_2.ys
									
										
									
									
									
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										15
									
								
								tests/verilog/localparam_no_default_2.ys
									
										
									
									
									
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			@ -0,0 +1,15 @@
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logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module;
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    localparam X = 1;
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endmodule
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EOF
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design -reset
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logger -expect error "localparam initialization is missing!" 1
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read_verilog <<EOF
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module Module;
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    localparam X;
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endmodule
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EOF
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										52
									
								
								tests/verilog/param_no_default.sv
									
										
									
									
									
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										52
									
								
								tests/verilog/param_no_default.sv
									
										
									
									
									
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			@ -0,0 +1,52 @@
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module example #(
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    parameter w,
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    parameter x = 1,
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    parameter byte y,
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    parameter byte z = 3
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) (
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    output a, b,
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    output byte c, d
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);
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    assign a = w;
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    assign b = x;
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    assign c = y;
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    assign d = z;
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endmodule
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module top;
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    wire a1, b1;
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    wire a2, b2;
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    wire a3, b3;
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    wire a4, b4;
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    byte c1, d1;
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    byte c2, d2;
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    byte c3, d3;
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    byte c4, d4;
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    example #(0, 1, 2) e1(a1, b1, c1, d1);
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    example #(.w(1), .y(4)) e2(a2, b2, c2, d2);
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    example #(.x(0), .w(1), .y(5)) e3(a3, b3, c3, d3);
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    example #(1, 0, 9, 10) e4(a4, b4, c4, d4);
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    always @* begin
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        assert (a1 == 0);
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        assert (b1 == 1);
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        assert (c1 == 2);
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        assert (d1 == 3);
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        assert (a2 == 1);
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        assert (b2 == 1);
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        assert (c2 == 4);
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        assert (d3 == 3);
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        assert (a3 == 1);
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        assert (b3 == 0);
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        assert (c3 == 5);
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        assert (d3 == 3);
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        assert (a4 == 1);
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        assert (b4 == 0);
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        assert (c4 == 9);
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        assert (d4 == 10);
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    end
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endmodule
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										7
									
								
								tests/verilog/param_no_default.ys
									
										
									
									
									
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										7
									
								
								tests/verilog/param_no_default.ys
									
										
									
									
									
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read_verilog -sv param_no_default.sv
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hierarchy
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proc
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flatten
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opt -full
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select -module top
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sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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										26
									
								
								tests/verilog/param_no_default_not_svmode.ys
									
										
									
									
									
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										26
									
								
								tests/verilog/param_no_default_not_svmode.ys
									
										
									
									
									
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logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module;
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    parameter X;
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endmodule
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EOF
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design -reset
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logger -expect-no-warnings
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read_verilog -sv <<EOF
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module Module #(
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    parameter X
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);
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endmodule
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EOF
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design -reset
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logger -expect error "Parameter defaults can only be omitted in SystemVerilog mode!" 1
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read_verilog <<EOF
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module Module #(
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    parameter X
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);
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endmodule
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EOF
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										12
									
								
								tests/verilog/param_no_default_unbound_1.ys
									
										
									
									
									
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										12
									
								
								tests/verilog/param_no_default_unbound_1.ys
									
										
									
									
									
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read_verilog -sv <<EOF
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module Example #(
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    parameter X
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);
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endmodule
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module top;
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    Example e();
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endmodule
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EOF
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logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
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hierarchy -top top
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										12
									
								
								tests/verilog/param_no_default_unbound_2.ys
									
										
									
									
									
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										12
									
								
								tests/verilog/param_no_default_unbound_2.ys
									
										
									
									
									
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read_verilog -sv <<EOF
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module Example #(
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    parameter X, Y
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);
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endmodule
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module top;
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    Example e();
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endmodule
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EOF
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logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
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hierarchy -top top
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										12
									
								
								tests/verilog/param_no_default_unbound_3.ys
									
										
									
									
									
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										12
									
								
								tests/verilog/param_no_default_unbound_3.ys
									
										
									
									
									
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read_verilog -sv <<EOF
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module Example #(
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    parameter X, Y
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);
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endmodule
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module top;
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    Example #(1) e();
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endmodule
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EOF
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logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1
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hierarchy -top top
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										12
									
								
								tests/verilog/param_no_default_unbound_4.ys
									
										
									
									
									
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										12
									
								
								tests/verilog/param_no_default_unbound_4.ys
									
										
									
									
									
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read_verilog -sv <<EOF
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module Example #(
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    parameter X, Y
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);
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endmodule
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module top;
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    Example #(.Y(1)) e();
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endmodule
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EOF
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logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
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hierarchy -top top
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										12
									
								
								tests/verilog/param_no_default_unbound_5.ys
									
										
									
									
									
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										12
									
								
								tests/verilog/param_no_default_unbound_5.ys
									
										
									
									
									
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read_verilog -sv <<EOF
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module Example #(
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    parameter X, Y = 2
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);
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endmodule
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module top;
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    Example #(.Y(1)) e();
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endmodule
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EOF
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logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
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hierarchy -top top
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