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	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
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					 1 changed files with 13 additions and 7 deletions
				
			
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					@ -1326,20 +1326,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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		{
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							{
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			if (width_hint < 0)
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								if (width_hint < 0)
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				detectSignWidth(width_hint, sign_hint);
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									detectSignWidth(width_hint, sign_hint);
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								is_signed = sign_hint;
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			RTLIL::SigSpec cond = children[0]->genRTLIL();
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								RTLIL::SigSpec cond = children[0]->genRTLIL();
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			RTLIL::SigSpec sig;
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								RTLIL::SigSpec sig;
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			if (cond.is_fully_const()) {
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								if (cond.is_fully_def())
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								{
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				if (cond.as_bool()) {
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									if (cond.as_bool()) {
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					sig = children[1]->genRTLIL(width_hint, sign_hint);
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										sig = children[1]->genRTLIL(width_hint, sign_hint);
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					widthExtend(this, sig, sig.size(), children[1]->is_signed);
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										log_assert(is_signed == children[1]->is_signed);
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				}
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									} else {
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				else {
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					sig = children[2]->genRTLIL(width_hint, sign_hint);
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										sig = children[2]->genRTLIL(width_hint, sign_hint);
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					widthExtend(this, sig, sig.size(), children[2]->is_signed);
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										log_assert(is_signed == children[2]->is_signed);
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				}
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									}
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									widthExtend(this, sig, sig.size(), is_signed);
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			}
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								}
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			else {
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								else
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								{
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				RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
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									RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
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				RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
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									RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
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					@ -1347,7 +1352,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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					cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
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										cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
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				int width = max(val1.size(), val2.size());
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									int width = max(val1.size(), val2.size());
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				is_signed = children[1]->is_signed && children[2]->is_signed;
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									log_assert(is_signed == children[1]->is_signed);
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									log_assert(is_signed == children[2]->is_signed);
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				widthExtend(this, val1, width, is_signed);
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									widthExtend(this, val1, width, is_signed);
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				widthExtend(this, val2, width, is_signed);
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									widthExtend(this, val2, width, is_signed);
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