mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-26 03:46:22 +00:00
Migrate build system to CMake
See #5895 for details. This commit does not include CI or documentation changes.
This commit is contained in:
parent
9d0cdb8551
commit
9b087b4aa7
207 changed files with 5202 additions and 2294 deletions
52
techlibs/intel/CMakeLists.txt
Normal file
52
techlibs/intel/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
yosys_pass(synth_intel
|
||||
synth_intel.cc
|
||||
REQUIRES
|
||||
abc
|
||||
abc9
|
||||
autoname
|
||||
blackbox
|
||||
check
|
||||
clean
|
||||
deminout
|
||||
dfflegalize
|
||||
flatten
|
||||
fsm
|
||||
hierarchy
|
||||
iopadmap
|
||||
memory
|
||||
memory_bram
|
||||
memory_map
|
||||
opt
|
||||
opt_clean
|
||||
opt_expr
|
||||
peepopt
|
||||
proc
|
||||
read_verilog
|
||||
setundef
|
||||
stat
|
||||
techmap
|
||||
tribuf
|
||||
wreduce
|
||||
write_blif
|
||||
write_verilog
|
||||
DATA_DIR
|
||||
intel
|
||||
DATA_FILES
|
||||
common/m9k_bb.v
|
||||
common/altpll_bb.v
|
||||
common/brams_m9k.txt
|
||||
common/brams_map_m9k.v
|
||||
common/ff_map.v
|
||||
|
||||
max10/cells_sim.v
|
||||
max10/cells_map.v
|
||||
|
||||
cyclone10lp/cells_sim.v
|
||||
cyclone10lp/cells_map.v
|
||||
|
||||
cycloneiv/cells_sim.v
|
||||
cycloneiv/cells_map.v
|
||||
|
||||
cycloneive/cells_sim.v
|
||||
cycloneive/cells_map.v
|
||||
)
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
|
||||
OBJS += techlibs/intel/synth_intel.o
|
||||
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
|
||||
|
||||
# Add the cell models and mappings for the VQM backend
|
||||
families := max10 cyclone10lp cycloneiv cycloneive
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
|
||||
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
|
||||
Loading…
Add table
Add a link
Reference in a new issue