mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 19:36:21 +00:00
Migrate build system to CMake
See #5895 for details. This commit does not include CI or documentation changes.
This commit is contained in:
Catherine
parent
9d0cdb8551
commit
9b087b4aa7
207 changed files with 5202 additions and 2294 deletions
2
techlibs/common/.gitignore
vendored
2
techlibs/common/.gitignore
vendored
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@ -1,2 +0,0 @@
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simlib_help.inc
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simcells_help.inc
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87
techlibs/common/CMakeLists.txt
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87
techlibs/common/CMakeLists.txt
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@ -0,0 +1,87 @@
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if (YOSYS_ENABLE_ABC)
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set(abc_requires abc abc9)
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endif()
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yosys_pass(synth
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synth.cc
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DEFINITIONS
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$<$<BOOL:${YOSYS_ENABLE_ABC}>:YOSYS_ENABLE_ABC>
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REQUIRES
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${abc_requires}
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alumacc
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arith_tree
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booth
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check
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clean
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flatten
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flowmap
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fsm
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hierarchy
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memory
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memory_map
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opt
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opt_clean
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opt_expr
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peepopt
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proc
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share
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stat
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techmap
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wreduce
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DATA_FILES
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simlib.v
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simcells.v
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techmap.v
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smtmap.v
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pmux2mux.v
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adff2dff.v
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dff2ff.v
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gate2lut.v
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cmp2lut.v
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mul2dsp.v
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abc9_model.v
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abc9_map.v
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abc9_unmap.v
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cmp2lcu.v
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cmp2softlogic.v
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choices/kogge-stone.v
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choices/han-carlson.v
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choices/sklansky.v
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)
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yosys_pass(prep
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prep.cc
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REQUIRES
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check
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flatten
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future
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hierarchy
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memory_collect
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memory_dff
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memory_memx
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opt
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opt_clean
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opt_expr
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proc
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sort
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stat
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wreduce
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)
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yosys_pass(opensta
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opensta.cc
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)
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yosys_pass(sdc_expand
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sdc_expand.cc
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REQUIRES
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chtype
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design
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hierarchy
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icell_liberty
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memory
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opensta
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proc
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read_verilog
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write_verilog
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)
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@ -1,41 +0,0 @@
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ifneq ($(SMALL),1)
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OBJS += techlibs/common/synth.o
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OBJS += techlibs/common/prep.o
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OBJS += techlibs/common/opensta.o
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OBJS += techlibs/common/sdc_expand.o
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endif
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GENFILES += techlibs/common/simlib_help.inc
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GENFILES += techlibs/common/simcells_help.inc
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techlibs/common/simlib_help.inc: techlibs/common/cellhelp.py techlibs/common/simlib.v
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$(Q) mkdir -p techlibs/common
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$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
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$(Q) mv $@.new $@
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techlibs/common/simcells_help.inc: techlibs/common/cellhelp.py techlibs/common/simcells.v
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$(Q) mkdir -p techlibs/common
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$(P) $(PYTHON_EXECUTABLE) $^ > $@.new
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$(Q) mv $@.new $@
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kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc
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$(eval $(call add_share_file,share,techlibs/common/simlib.v))
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$(eval $(call add_share_file,share,techlibs/common/simcells.v))
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$(eval $(call add_share_file,share,techlibs/common/techmap.v))
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$(eval $(call add_share_file,share,techlibs/common/smtmap.v))
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$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
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$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
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$(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
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$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
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$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
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$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
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$(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
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$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
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$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
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$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
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$(eval $(call add_share_file,share/choices,techlibs/common/choices/sklansky.v))
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@ -1,100 +0,0 @@
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#!/usr/bin/env python3
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from __future__ import annotations
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import fileinput
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import json
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from pathlib import Path
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class SimHelper:
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name: str = ""
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title: str = ""
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ports: str = ""
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source: str = ""
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desc: list[str]
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code: list[str]
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group: str = ""
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ver: str = "1"
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tags: list[str]
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def __init__(self) -> None:
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self.desc = []
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self.tags = []
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def __str__(self) -> str:
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printed_fields = [
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"name", "title", "ports", "source", "desc", "code", "group", "ver",
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"tags",
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]
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# generate C++ struct
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val = f"cell_help[{json.dumps(self.name)}] = "
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val += "{\n"
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for field in printed_fields:
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field_val = getattr(self, field)
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if isinstance(field_val, list):
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field_val = "\n".join(field_val)
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field_val = field_val.strip()
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val += f' {json.dumps(field_val)},\n'
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val += "};\n"
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return val
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def simcells_reparse(cell: SimHelper):
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# cut manual signature
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cell.desc = cell.desc[3:]
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# code-block truth table
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new_desc = []
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indent = ""
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for line in cell.desc:
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if line.startswith("Truth table:"):
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indent = " "
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new_desc.pop()
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new_desc.extend(["::", ""])
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new_desc.append(indent + line)
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cell.desc = new_desc
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# set version
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cell.ver = "2a"
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simHelper = SimHelper()
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for line in fileinput.input():
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line = line.rstrip()
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# special comments
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if line.startswith("//-"):
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simHelper.desc.append(line[4:] if len(line) > 4 else "")
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elif line.startswith("//* "):
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_, key, val = line.split(maxsplit=2)
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setattr(simHelper, key, val)
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# code parsing
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if line.startswith("module "):
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clean_line = line[7:].replace("\\", "").replace(";", "")
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simHelper.name, simHelper.ports = clean_line.split(maxsplit=1)
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simHelper.code = []
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short_filename = Path(fileinput.filename()).name
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simHelper.source = f'{short_filename}:{fileinput.filelineno()}'
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elif not line.startswith("endmodule"):
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line = " " + line
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try:
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simHelper.code.append(line.replace("\t", " "))
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except AttributeError:
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# no module definition, ignore line
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pass
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if line.startswith("endmodule"):
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short_filename = Path(fileinput.filename()).name
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if simHelper.ver == "1" and short_filename == "simcells.v":
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# default simcells parsing
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simcells_reparse(simHelper)
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# check help
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if simHelper.desc and simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith(' '):
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simHelper.desc.pop(1)
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# check group
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assert simHelper.group, f"techlibs/common/{simHelper.source}: {simHelper.name} cell missing group"
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# dump
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print(simHelper)
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# new
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simHelper = SimHelper()
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@ -5,7 +5,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#if !defined(YOSYS_DISABLE_SPAWN)
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#if defined(YOSYS_ENABLE_SPAWN)
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struct OpenstaPass : public Pass
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{
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OpenstaPass() : Pass("opensta", "run OpenSTA") { }
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