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Migrate build system to CMake

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See #5895 for details.

This commit does not include CI or documentation changes.
This commit is contained in:
Catherine 2026-05-12 05:33:04 +00:00
parent 9d0cdb8551
commit 9b087b4aa7
207 changed files with 5202 additions and 2294 deletions
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70
frontends/verific/CMakeLists.txt Normal file
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if (NOT YOSYS_ENABLE_VERIFIC)
# Stub interface library.
add_library(verific INTERFACE)
set(verific_data_files)
else()
if (NOT YOSYS_VERIFIC_COMPONENTS)
get_verific_components(YOSYS_VERIFIC_COMPONENTS)
endif()
if (NOT YOSYS_VERIFIC_FEATURES)
foreach (component ${YOSYS_VERIFIC_COMPONENTS})
if (component MATCHES "^(hier_tree|vhdl|edif|extensions)$")
list(APPEND YOSYS_VERIFIC_FEATURES ${component})
elseif (component STREQUAL "verilog")
list(APPEND YOSYS_VERIFIC_FEATURES systemverilog)
elseif (component STREQUAL "synlib")
list(APPEND YOSYS_VERIFIC_FEATURES liberty)
endif()
endforeach()
endif()
message(STATUS "Verific library components: ${YOSYS_VERIFIC_COMPONENTS}")
message(STATUS "Verific frontend features: ${YOSYS_VERIFIC_FEATURES}")
get_verific_options(verific_include_dirs verific_libraries ${YOSYS_VERIFIC_COMPONENTS})
add_library(verific INTERFACE)
target_include_directories(verific INTERFACE
${verific_include_dirs}
)
target_link_libraries(verific INTERFACE
$<LINK_LIBRARY:WHOLE_ARCHIVE,${verific_libraries}>
PkgConfig::zlib
)
set(verific_data_files)
if ("vhdl" IN_LIST YOSYS_VERIFIC_FEATURES)
foreach (vdb_std 1987 1993 2008 2019)
set(vdb_std_root ${YOSYS_VERIFIC_DIR}/vhdl_packages/vdbs_${vdb_std})
file(GLOB_RECURSE vdb_files RELATIVE ${vdb_std_root} ${vdb_std_root}/*)
foreach (vdb_file ${vdb_files})
list(APPEND verific_data_files
verific/vhdl_vdbs_${vdb_std}/${vdb_file}
${YOSYS_VERIFIC_DIR}/vhdl_packages/vdbs_${vdb_std}/${vdb_file}
)
endforeach()
endforeach()
endif()
endif()
yosys_frontend(verific
verific.cc
verific.h
$<${YOSYS_ENABLE_VERIFIC}:verificsva.cc>
DEFINITIONS
$<$<IN_LIST:hier_tree,${YOSYS_VERIFIC_FEATURES}>:VERIFIC_HIER_TREE_SUPPORT>
$<$<IN_LIST:systemverilog,${YOSYS_VERIFIC_FEATURES}>:VERIFIC_SYSTEMVERILOG_SUPPORT>
$<$<IN_LIST:vhdl,${YOSYS_VERIFIC_FEATURES}>:VERIFIC_VHDL_SUPPORT>
$<$<IN_LIST:edif,${YOSYS_VERIFIC_FEATURES}>:VERIFIC_EDIF_SUPPORT>
$<$<IN_LIST:liberty,${YOSYS_VERIFIC_FEATURES}>:VERIFIC_LIBERTY_SUPPORT>
$<$<IN_LIST:extensions,${YOSYS_VERIFIC_FEATURES}>:YOSYSHQ_VERIFIC_EXTENSIONS>
LIBRARIES
verific
REQUIRES
sha1
read_verilog
PROVIDES
read
DATA_EXPLICIT
${verific_data_files}
)

23
frontends/verific/Makefile.inc
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@ -1,23 +0,0 @@
OBJS += frontends/verific/verific.o
ifeq ($(ENABLE_VERIFIC),1)
OBJS += frontends/verific/verificsva.o
EXTRA_TARGETS += share/verific
share/verific:
$(P) rm -rf share/verific.new
$(Q) mkdir -p share/verific.new
ifeq ($(ENABLE_VERIFIC_VHDL),1)
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2019/. share/verific.new/vhdl_vdbs_2019
endif
$(Q) chmod -R a+rX share/verific.new
$(Q) mv share/verific.new share/verific
endif