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abstract: -state allow partial abstraction, don't use buffer-normalized mode
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2 changed files with 109 additions and 49 deletions
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@ -15,6 +15,27 @@ abstract -state -enablen magic
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check -assert
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# show -prefix after_base
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design -reset
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read_verilog <<EOT
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module fff (CLK, DDD, QQQ, Q, magic);
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input CLK;
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input [2:0] DDD;
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output reg [2:0] QQQ;
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output reg Q;
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input magic;
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always @(posedge CLK)
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QQQ <= DDD;
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assign Q = QQQ[0];
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endmodule
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EOT
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proc
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# show -prefix before_wide
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abstract -state -enablen magic w:Q
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# show -prefix after_wide
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check -assert
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design -reset
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read_verilog <<EOT
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module half_clock_en (CLK, E, Q, magic);
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