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Fine tune ice40_dsp.pmg, add support for packing subsets of registers
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8f0e796be1
commit
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4 changed files with 47 additions and 35 deletions
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@ -1,7 +1,7 @@
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pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> P_used
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state <SigSpec> sigPused
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match dsp
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select dsp->type.in(\DSP48E1)
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@ -43,23 +43,23 @@ endcode
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// Extract the bits of P that actually have a consumer
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// (as opposed to being a sign extension)
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code P_used
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code sigPused
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SigSpec P = port(dsp, \P);
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int i;
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for (i = GetSize(P); i > 0; i--)
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if (nusers(P[i-1]) > 1)
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break;
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P_used = P.extract(0, i).remove_const();
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sigPused = P.extract(0, i).remove_const();
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endcode
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match ffP
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if !P_used.empty()
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if !sigPused.empty()
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select ffP->type.in($dff, $dffe)
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select nusers(port(ffP, \D)) == 2
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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filter param(ffP, \WIDTH).as_int() >= GetSize(P_used)
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filter includes(port(ffP, \D).to_sigbit_set(), P_used.to_sigbit_set())
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filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
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filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
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optional
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endmatch
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@ -68,12 +68,12 @@ endmatch
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// since that would lose information helpful for
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// efficient wide-mux inference
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match muxP
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if !P_used.empty() && !ffP
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if !sigPused.empty() && !ffP
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select muxP->type.in($mux)
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select nusers(port(muxP, \B)) == 2
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select port(muxP, \A).is_fully_undef()
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filter param(muxP, \WIDTH).as_int() >= GetSize(P_used)
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filter includes(port(muxP, \B).to_sigbit_set(), P_used.to_sigbit_set())
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filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
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filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
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optional
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endmatch
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@ -83,7 +83,7 @@ match ffY
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select nusers(port(ffY, \D)) == 2
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// DSP48E1 does not support clock inversion
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select param(ffY, \CLK_POLARITY).as_bool()
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filter param(ffY, \WIDTH).as_int() >= GetSize(P_used)
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filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
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filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
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endmatch
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