mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-15 14:11:29 +00:00
Code Activity

Fine tune ice40_dsp.pmg, add support for packing subsets of registers

Browse source
This commit is contained in:
Eddie Hung 2019-07-19 10:57:32 -07:00
parent 8f0e796be1
commit 9ad11ea2cc
4 changed files with 47 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

7
passes/pmgen/ice40_dsp.cc
View file

@ -23,13 +23,16 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
template<class T> bool includes(const T &lhs, const T &rhs) {
return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
}
#include "passes/pmgen/ice40_dsp_pm.h"
void create_ice40_dsp(ice40_dsp_pm &pm)
{
auto &st = pm.st_ice40_dsp;
#if 0
#if 1
log("\n");
log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--"));
@ -100,7 +103,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort("\\IRSTTOP", State::S0);
cell->setPort("\\IRSTBOT", State::S0);
if (st.clock_vld)
if (st.clock != SigBit())
{
cell->setPort("\\CLK", st.clock);
cell->setPort("\\CE", State::S1);