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Add "dffinit -highlow" and fix synth_intel

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-01-09 18:42:19 +01:00
parent a96c775a73
commit 9ac560f5d3
2 changed files with 21 additions and 1 deletions
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20
passes/techmap/dffinit.cc
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@ -38,15 +38,25 @@ struct DffinitPass : public Pass {
log(" operate on the specified cell type. this option can be used\n");
log(" multiple times.\n");
log("\n");
log(" -highlow\n");
log(" use the string values \"high\" and \"low\" to represent a single-bit\n");
log(" initial value of 1 or 0. (multi-bit values are not supported in this\n");
log(" mode.)\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
dict<IdString, dict<IdString, IdString>> ff_types;
bool highlow_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-highlow") {
highlow_mode = true;
continue;
}
if (args[argidx] == "-ff" && argidx+3 < args.size()) {
IdString cell_name = RTLIL::escape_id(args[++argidx]);
IdString output_port = RTLIL::escape_id(args[++argidx]);
@ -106,6 +116,16 @@ struct DffinitPass : public Pass {
cleanup_bits.insert(sig[i]);
}
if (highlow_mode && GetSize(value) != 0) {
if (GetSize(value) != 1)
log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
log_id(module), log_id(cell), log_id(it.second));
if (value[0] == State::S1)
value = Const("high");
else
value = Const("low");
}
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),
log_id(it.first), log_signal(sig), log_signal(value));
cell->setParam(it.second, value);