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Finished presentation intro
Also some other tidy up.
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@ -4,6 +4,6 @@ Using Yosys (advanced)
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.. toctree::
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:maxdepth: 2
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more_scripting
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more_scripting/index
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memory_mapping
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yosys_flows
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@ -5,4 +5,5 @@ More scripting
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opt_passes
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selections
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synth
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troubleshooting
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@ -11,26 +11,26 @@ This chapter outlines these optimizations.
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Simple optimizations
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--------------------
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The Yosys pass opt runs a number of simple optimizations. This includes removing
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The Yosys pass ``opt`` runs a number of simple optimizations. This includes removing
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unused signals and cells and const folding. It is recommended to run this pass
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after each major step in the synthesis script. At the time of this writing the
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opt pass executes the following passes that each perform a simple optimization:
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``opt`` pass executes the following passes that each perform a simple optimization:
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- Once at the beginning of opt:
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- Once at the beginning of ``opt``:
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- opt_expr
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- opt_merge -nomux
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- ``opt_expr``
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- ``opt_merge -nomux``
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- Repeat until result is stable:
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- opt_muxtree
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- opt_reduce
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- opt_merge
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- opt_rmdff
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- opt_clean
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- opt_expr
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- ``opt_muxtree``
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- ``opt_reduce``
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- ``opt_merge``
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- ``opt_rmdff``
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- ``opt_clean``
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- ``opt_expr``
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The following section describes each of the opt\_ passes.
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The following section describes each of the ``opt_`` passes.
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The opt_expr pass
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~~~~~~~~~~~~~~~~~
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@ -40,7 +40,7 @@ described in :ref:`chapter:celllib`. This means a cell with all
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constant inputs is replaced with the constant value this cell drives. In some
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cases this pass can also optimize cells with some constant inputs.
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.. table:: Const folding rules for $_AND\_ cells as used in opt_expr.
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.. table:: Const folding rules for ``$_AND_`` cells as used in opt_expr.
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:name: tab:opt_expr_and
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:align: center
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@ -65,26 +65,26 @@ cases this pass can also optimize cells with some constant inputs.
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.. How to format table?
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:numref:`Table %s <tab:opt_expr_and>` shows the replacement rules used for
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optimizing an $_AND\_ gate. The first three rules implement the obvious const
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folding rules. Note that ‘any' might include dynamic values calculated by other
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optimizing an ``$_AND_`` gate. The first three rules implement the obvious const
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folding rules. Note that 'any' might include dynamic values calculated by other
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parts of the circuit. The following three lines propagate undef (X) states.
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These are the only three cases in which it is allowed to propagate an undef
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according to Sec. 5.1.10 of IEEE Std. 1364-2005 :cite:p:`Verilog2005`.
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The next two lines assume the value 0 for undef states. These two rules are only
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used if no other substitutions are possible in the current module. If other
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substitutions are possible they are performed first, in the hope that the ‘any'
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substitutions are possible they are performed first, in the hope that the 'any'
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will change to an undef value or a 1 and therefore the output can be set to
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undef.
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The last two lines simply replace an $_AND\_ gate with one constant-1 input with
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a buffer.
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The last two lines simply replace an ``$_AND_`` gate with one constant-1 input
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with a buffer.
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Besides this basic const folding the opt_expr pass can replace 1-bit wide $eq
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and $ne cells with buffers or not-gates if one input is constant.
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Besides this basic const folding the opt_expr pass can replace 1-bit wide
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``$eq`` and ``$ne`` cells with buffers or not-gates if one input is constant.
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The opt_expr pass is very conservative regarding optimizing $mux cells, as these
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cells are often used to model decision-trees and breaking these trees can
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The opt_expr pass is very conservative regarding optimizing ``$mux`` cells, as
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these cells are often used to model decision-trees and breaking these trees can
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interfere with other optimizations.
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The opt_muxtree pass
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@ -107,16 +107,16 @@ The opt_reduce pass
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~~~~~~~~~~~~~~~~~~~
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This is a simple optimization pass that identifies and consolidates identical
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input bits to $reduce_and and $reduce_or cells. It also sorts the input bits to
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ease identification of shareable $reduce_and and $reduce_or cells in other
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passes.
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input bits to ``$reduce_and`` and ``$reduce_or`` cells. It also sorts the input
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bits to ease identification of shareable ``$reduce_and`` and ``$reduce_or``
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cells in other passes.
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This pass also identifies and consolidates identical inputs to multiplexer
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cells. In this case the new shared select bit is driven using a $reduce_or cell
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that combines the original select bits.
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cells. In this case the new shared select bit is driven using a ``$reduce_or``
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cell that combines the original select bits.
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Lastly this pass consolidates trees of $reduce_and cells and trees of $reduce_or
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cells to single large $reduce_and or $reduce_or cells.
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Lastly this pass consolidates trees of ``$reduce_and`` cells and trees of
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``$reduce_or`` cells to single large ``$reduce_and`` or ``$reduce_or`` cells.
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These three simple optimizations are performed in a loop until a stable result
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is produced.
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@ -124,8 +124,9 @@ is produced.
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The opt_rmdff pass
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~~~~~~~~~~~~~~~~~~
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This pass identifies single-bit d-type flip-flops ($_DFF\_, $dff, and $adff
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cells) with a constant data input and replaces them with a constant driver.
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This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and
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``$adff`` cells) with a constant data input and replaces them with a constant
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driver.
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The opt_clean pass
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~~~~~~~~~~~~~~~~~~
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@ -141,9 +142,10 @@ This pass performs trivial resource sharing. This means that this pass
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identifies cells with identical inputs and replaces them with a single instance
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of the cell.
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The option -nomux can be used to disable resource sharing for multiplexer cells
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($mux and $pmux. This can be useful as it prevents multiplexer trees to be
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merged, which might prevent opt_muxtree to identify possible optimizations.
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The option ``-nomux`` can be used to disable resource sharing for multiplexer
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cells (``$mux`` and ``$pmux.`` This can be useful as it prevents multiplexer
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trees to be merged, which might prevent ``opt_muxtree`` to identify possible
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optimizations.
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FSM extraction and encoding
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---------------------------
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@ -187,12 +189,12 @@ fsm pass simply executes the following other passes:
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The fsm_detect pass identifies FSM state registers and marks them using the
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``\fsm_encoding = "auto"`` attribute. The fsm_extract extracts all FSMs marked
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using the ``\fsm_encoding`` attribute (unless ``\fsm_encoding`` is set to
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"none") and replaces the corresponding RTL cells with a $fsm cell. All other
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fsm\_ passes operate on these $fsm cells. The fsm_map call finally replaces the
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$fsm cells with RTL cells.
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"none") and replaces the corresponding RTL cells with a ``$fsm`` cell. All other
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``fsm_`` passes operate on these ``$fsm`` cells. The fsm_map call finally
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replaces the ``$fsm`` cells with RTL cells.
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Note that these optimizations operate on an RTL netlist. I.e. the fsm pass
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should be executed after the proc pass has transformed all RTLIL::Process
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Note that these optimizations operate on an RTL netlist. I.e. the ``fsm`` pass
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should be executed after the proc pass has transformed all ``RTLIL::Process``
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objects to RTL cells.
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The algorithms used for FSM detection and extraction are influenced by a more
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@ -207,11 +209,12 @@ description:
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- Does not already have the ``\fsm_encoding`` attribute.
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- Is not an output of the containing module.
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- Is driven by single $dff or $adff cell.
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- The ``\D``-Input of this $dff or $adff cell is driven by a multiplexer tree
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that only has constants or the old state value on its leaves.
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- Is driven by single ``$dff`` or ``$adff`` cell.
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- The ``\D``-Input of this ``$dff`` or ``$adff`` cell is driven by a
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multiplexer tree that only has constants or the old state value on its
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leaves.
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- The state value is only used in the said multiplexer tree or by simple
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relational cells that compare the state value to a constant (usually $eq
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relational cells that compare the state value to a constant (usually ``$eq``
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cells).
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This heuristic has proven to work very well. It is possible to overwrite it by
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@ -246,10 +249,10 @@ information is determined:
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The state registers (and asynchronous reset state, if applicable) is simply
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determined by identifying the driver for the state signal.
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From there the $mux-tree driving the state register inputs is recursively
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traversed. All select inputs are control signals and the leaves of the $mux-tree
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are the states. The algorithm fails if a non-constant leaf that is not the state
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signal itself is found.
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From there the ``$mux-tree`` driving the state register inputs is recursively
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traversed. All select inputs are control signals and the leaves of the
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``$mux-tree`` are the states. The algorithm fails if a non-constant leaf that is
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not the state signal itself is found.
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The list of control outputs is initialized with the bits from the state signal.
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It is then extended by adding all values that are calculated by cells that
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@ -281,17 +284,17 @@ transition table. For each state:
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6. If step 4 was successful: Emit transition
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Finally a $fsm cell is created with the generated transition table and added to
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the module. This new cell is connected to the control signals and the old
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Finally a ``$fsm`` cell is created with the generated transition table and added
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to the module. This new cell is connected to the control signals and the old
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drivers for the control outputs are disconnected.
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FSM optimization
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~~~~~~~~~~~~~~~~
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The fsm_opt pass performs basic optimizations on $fsm cells (not including state
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recoding). The following optimizations are performed (in this order):
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The fsm_opt pass performs basic optimizations on ``$fsm`` cells (not including
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state recoding). The following optimizations are performed (in this order):
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- Unused control outputs are removed from the $fsm cell. The attribute
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- Unused control outputs are removed from the ``$fsm`` cell. The attribute
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``\unused_bits`` (that is usually set by the opt_clean pass) is used to
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determine which control outputs are unused.
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9
docs/source/using_yosys/more_scripting/synth.rst
Normal file
9
docs/source/using_yosys/more_scripting/synth.rst
Normal file
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Introduction to synthesis
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-------------------------
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The following commands are executed by the ``synth`` command:
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.. literalinclude:: /cmd/synth.rst
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:start-at: begin:
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:end-before: .. raw:: latex
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:dedent:
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