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https://github.com/YosysHQ/yosys
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Replace opt_rmdff with opt_dff.
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commit
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18 changed files with 75 additions and 73 deletions
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@ -15,6 +15,5 @@ proc
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT3
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
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select -assert-none t:AL_MAP_SEQ %% t:* %D
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@ -10,8 +10,8 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:L6MUX21
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select -assert-count 15 t:LUT4
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select -assert-count 6 t:PFUMX
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select -assert-max 1 t:L6MUX21
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select -assert-max 16 t:LUT4
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select -assert-max 7 t:PFUMX
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select -assert-count 6 t:TRELLIS_FF
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select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
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@ -32,9 +32,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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design -load read
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@ -45,6 +44,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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@ -19,6 +19,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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@ -45,24 +45,25 @@ flatten
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synth_gowin -run coarse:
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# check the flops mapped as expected
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select -assert-count 1 t:DFF
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select -assert-count 2 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 0 t:DFFE
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select -assert-count 2 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 0 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 0 t:DFFNR
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select -assert-count 0 t:DFFNRE
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select -assert-count 2 t:DFFNS
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select -assert-count 2 t:DFFNSE
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select -assert-count 3 t:DFFNS
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select -assert-count 1 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 0 t:DFFR
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select -assert-count 0 t:DFFRE
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select -assert-count 2 t:DFFS
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select -assert-count 2 t:DFFSE
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select -assert-count 12 t:LUT2
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select -assert-count 3 t:DFFS
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select -assert-count 1 t:DFFSE
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select -assert-count 4 t:LUT2
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select -assert-count 4 t:LUT4
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@ -77,10 +77,9 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 1 t:MISTRAL_ALUT2
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 %% t:* %D
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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design -load read
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@ -90,7 +89,6 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 1 t:MISTRAL_ALUT2
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 %% t:* %D
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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@ -12,12 +12,13 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 1 t:MISTRAL_NOT
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select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-max 1 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 1 t:MISTRAL_ALUT3
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select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
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select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -reset
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read_verilog ../common/fsm.v
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@ -34,9 +35,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 1 t:MISTRAL_NOT
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select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
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select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
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select -assert-max 1 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
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select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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@ -193,13 +193,13 @@ do
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elif [ "$frontend" = "verific_gates" ]; then
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test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;"
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else
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext}
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.${refext}
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test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
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if [ -n "$firrtl2verilog" ]; then
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if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
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"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
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"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
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$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
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fi
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fi
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fi
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