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Added Verilog parser support for asserts

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Clifford Wolf 2014-01-19 04:18:22 +01:00
parent 3d7a1491aa
commit 9a1eb45c75
4 changed files with 12 additions and 3 deletions
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frontends/verilog/lexer.l
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@ -113,6 +113,8 @@ namespace VERILOG_FRONTEND {
"generate" { return TOK_GENERATE; }
"endgenerate" { return TOK_ENDGENERATE; }
"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; }
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }