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Added Verilog parser support for asserts

This commit is contained in:
Clifford Wolf 2014-01-19 04:18:22 +01:00
parent 3d7a1491aa
commit 9a1eb45c75
4 changed files with 12 additions and 3 deletions

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@ -58,6 +58,7 @@ namespace AST
AST_CELLTYPE,
AST_IDENTIFIER,
AST_PREFIX,
AST_ASSERT,
AST_FCALL,
AST_TO_SIGNED,