mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-15 12:00:28 +00:00
Code Activity

Merge pull request #5386 from YosysHQ/emil/liberty-glob-all

Browse source 
Expand wildcards in Liberty file consumers
This commit is contained in:
Emil J 2025-10-09 20:21:48 +02:00 • committed by GitHub
commit 9a12d92551
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
8 changed files with 14 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/liberty/libcache.ys
View file

@ -1,5 +1,5 @@
libcache -verbose
libcache -enable busdef.lib
libcache -enable bus*f.lib
logger -expect log "Caching is disabled by default." 1
logger -expect log "Caching is enabled for `busdef.lib'." 1

2
tests/techmap/clockgate.ys
View file

@ -194,7 +194,7 @@ select -assert-count 1 t:\\pdk_icg
#------------------------------------------------------------------------------
design -load before
clockgate -liberty clockgate.lib
clockgate -liberty c*ckgate.lib
# rising edge ICGs
select -module dffe_00 -assert-count 0 t:\\pos_small

2
tests/techmap/dfflibmap.ys
View file

@ -23,7 +23,7 @@ read_liberty -lib dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -prepare -liberty dffl*bmap.lib
equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
design -load orig