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Fixed mem assignment in left-hand-side concatenation

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This commit is contained in:
Clifford Wolf 2016-07-08 14:31:06 +02:00
parent b782076698
commit 9a101dc1f7
2 changed files with 57 additions and 0 deletions
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13
tests/simple/memory.v
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@ -264,3 +264,16 @@ module memtest11(clk, wen, waddr, raddr, wdata, rdata);
end
endmodule
// ----------------------------------------------------------
module memtest12 (
input clk,
input [1:0] adr,
input [1:0] din,
output reg [1:0] q
);
reg [1:0] ram [3:0];
always@(posedge clk)
{ram[adr], q} <= {din, ram[adr]};
endmodule