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Defer redirecting cell outputs when merging cells in opt_merge until after we've done a full pass over the cells.

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This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
This commit is contained in:
Robert O'Callahan 2025-12-19 00:38:47 +00:00
parent 64a933d77b
commit 9a0f94faa4
1 changed files with 10 additions and 6 deletions
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16
passes/opt/opt_merge.cc
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@ -284,6 +284,7 @@ struct OptMergeWorker
CellPtrHash,
CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
std::vector<RTLIL::SigSig> redirects;
for (auto cell : cells)
{
auto [cell_in_map, inserted] = known_cells.insert(cell);
@ -305,12 +306,7 @@ struct OptMergeWorker
RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
log_debug(" Redirecting output %s: %s = %s\n", it.first,
log_signal(it.second), log_signal(other_sig));
Const init = initvals(other_sig);
initvals.remove_init(it.second);
initvals.remove_init(other_sig);
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
initvals.set_init(other_sig, init);
redirects.push_back(RTLIL::SigSig(it.second, std::move(other_sig)));
}
}
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
@ -318,6 +314,14 @@ struct OptMergeWorker
total_count++;
}
}
for (const RTLIL::SigSig &redirect : redirects) {
module->connect(redirect);
Const init = initvals(redirect.second);
initvals.remove_init(redirect.first);
initvals.remove_init(redirect.second);
assign_map.add(redirect.first, redirect.second);
initvals.set_init(redirect.second, init);
}
}
log_suppressed();